1. Technical Field
The present invention relates in general to a fetch and store buffer scheme and, in particular, to a fetch and store buffer scheme which supports out of order execution in a superscalar processor design.
2. Description of the Related Art
The particular function obtained by any computer is dependant on the instruction sequence of its computer program. Thus, a computer program is expected to handle its instructions, and their associated fetches and stores to memory, in the sequence indicated by the instruction sequence. Otherwise, memory incoherence may result. Consequently, conventional CPUs maintain the instruction sequence of fetches and stores during program execution to provide the program results which the program designer expects of the program.
To avoid violating the instruction sequence as programmed by the computer programmer, prior computer systems maintain the instruction sequence by not starting the execution of the next instruction in a program until the execution was complete for the adjacent prior instruction in the program sequence. Thus, a memory fetch or a store for a next instruction in the program sequence was delayed until execution was completed for the prior instruction in the program sequence. All memory fetches and stores within any instruction were executed in the order specified by the architecture of the respective instruction.
Clearly, system performance would be enhanced if store and fetch requests are issued to storage as soon as the request is in a proper form to be issued, rather than being delayed until their proper position in the program sequence. However, because particular store and fetch requests will be generated faster than others, such a scheme will create out of sequence execution.
This problem becomes more pronounced in a superscalar environment. When two or more execution units are accessing a memory unit, the likelihood of copending dependent store and fetch requests substantially increases. In order to implement such a scheme without introducing hazardous memory operations, it would be desirable to have a fetch and store buffer scheme which supports such out of order execution while maintaining memory coherence as expected by the instruction sequence. Lastly, the problem also applies in a multiprocessor system when two or more processors are accessing memory.